Dual-directional electrostatic discharge protection method

ABSTRACT

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. 
     Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. 
     Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.

BACKGROUND OF THE INVENTION

The present invention relates to an electrostatic discharge protectionstructure.

It is well known that semiconductor Integrated Circuits (IC) may bedamaged by Electro-Static Discharge (ESD). Four different causes areidentified to be responsible for the ESD phenomenon. The first cause,due to the human-body, results from electrostatic stress exerted on anIC when a human carrying electrostatic charges touches the lead pins ofthe IC. The second cause, due to handling by a machine, results fromelectrostatic discharge that occurs when a machine carryingelectrostatic charges comes into contact with the lead pins of an IC.The third cause, due to charged devices, results from the ESD currentspike generated when an IC lead pins carrying electrostatic charges aregrounded during the handling of the IC. The fourth cause, due to inducedelectric fields, results from the electric field that an IC is exposedto which may produce an ESD in the IC when the IC is later grounded.

Efforts directed at scaling down CMOS processing technologies in orderto produce ICs containing transistors with thinner gate oxides and everdecreasing channel dimensions must go hand in hand with development ofnew structures to protect the ICs against ESD. Therefore, the needcontinues to exist to reliably protect deep submicron CMOS ICs from thepotential damages of ESD.

A well known structure for protecting an IC against ESD damage is aSemiconductor Controlled Rectifier (SCR), also known as a thyristor.FIG. 1A shows a cross-sectional view of a typical lateral SCR 10 whichhas an anode terminal 12 and a cathode terminal 14. FIG. 1B shows acircuit schematic representation of SCR 10. As is seen from FIG. 1B, SCR10 is composed of an npn bipolar transistor 32, a pnp bipolar transistor30 and two parasitic resistors 34 and 36. In order to turn on SCR 10, apositive voltage must be applied between anode terminal 12 and cathodeterminal 14 to forward bias both transistors 30 and 32. When SCR 10turns on, a low impedance discharge path forms between the two terminalsof SCR 10 to discharge the current.

FIG. 1C shows the current-voltage characteristic of SCR 10. In FIG. 1C,the vertical axis represents the current flow between terminals 12 and14, and the horizontal axis represents the voltage across terminals 12and 14 of SCR 10. The voltage at which SCR 10 enters the regioncharacterized by a negative current-voltage relationship is called thesnap-back or the trigger voltage, which is shown in FIG. 1C as V_(t).

A major disadvantage of SCR 10 is that it provides protection againstESD in only one direction, i.e. either against a positivevoltage/current pulse or against a negative voltage/current pulse.Consequently, to protect an IC against ESD, one SCR must be disposedbetween each input/output pad of the IC and the positive supply voltageand one SCR must be disposed between each input/output pad and thenegative supply voltage. Alternatively, an IC is protected against ESDdamage by a SCR which provides an active discharge path in one supplydirection (positive or negative) and which provides a discharge paththrough parasitic diodes in the other supply direction. Therefore, whatis needed is a single ESD protection structure capable of protecting anIC against both positive and negatives ESD pulses.

FIG. 1D shows a top view of SCR 10 constructed using conventional layouttechniques. The rectangular shape of p⁺ region 20 or n⁺ region 22 isknown in the art as a finger structure. When an ESD pulse appears acrossanode terminal 12 and cathode terminal 14, current enters into ordeparts from p⁺ region 20 and n⁺ regions 22 from across only a singleedge of each of the fingers, designated in FIG. 1D with solid arrows 30.In order to increase the current handling capability—hence to improvethe ESD performance of SCR 10—prior art layout techniques add more n⁺fingers in p-type substrate 24 and more p⁺ fingers in n-well 26.However, by thus adding more p⁺ and n⁺ fingers, a significant amount ofsemiconductor surface area is occupied without a proportional increasein the ESD performance of the resulting structure. This is because, thecurrent flow between each pair of newly added p⁺ and n⁺ fingers islimited to a component crossing only a single edge of each of the addedfingers. It is, therefore, advantageous to develop an ESD layoutstructure which provides for current flow across more edges of the p⁺and n⁺ finger.

Referring to FIG. 1A, the trigger voltage, V_(t), of SCR 10 depends onthe concentration profile of the impurities that form the n-type and thep-type semiconductor regions of SCR 10. Therefore, once SCR 10 isfabricated using a conventional IC fabrication process technology, itstrigger voltage cannot be changed.

Often an IC includes several subcircuits which operate at differentsupply voltages. For example, some blocks of circuitry within an IC mayrequire five volts to operate, while other blocks of circuitry withinthe same IC may require fifteen volts to operate. Because SCR 10 has afixed trigger voltage, it is not suitable for use as an ESD protectiondevice in a multi-supply voltage IC. To protect a multi-supply voltageIC against ESD, prior art techniques use different ESD protectionstructures that trigger at different voltages. It is, therefore,advantageous to have a single ESD structure whose trigger voltage isvaried to accommodate for ESD protection at different supply voltages.

SUMMARY OF THE INVENTION

An Electro-Static Discharge (ESD) protection structure, in accordancewith the present invention, protects an Integrated Circuit (IC) againstboth positive and negative ESD pulses.

The ESD protection structure has an anode terminal and a cathodeterminal and is composed of five semiconductor regions to form ann-p-n-p-n device. The ESD structure, hence, includes one pnp bipolartransistor, two npn bipolar transistors and four parasitic resistors.

When the voltage potential of an ESD pulse appearing across the twoterminals of the ESD protection structure exceeds the reverse breakdownvoltage of the collector-base junction of the pnp transistor,electron-hole pairs are generated. The holes thus generated flow towardthe cathode terminal, forcing the npn transistor whose emitter region isconnected to the cathode terminal to turn on. Subsequently, the ESDprotection structure enters into a snap-back mode, thereby, to form alow impedance current discharge path between the two terminals todischarge the ESD current. The trigger voltage of the ESD protectionstructure of the present invention is hence determined by thereverse-breakdown voltage of the collector-base junction of the pnptransistor.

Some embodiments of the ESD protection structure of the presentinvention are formed by combining a number of standard cells, inaccordance with the present invention. The standard cells which includea center cell, an edge cell and a corner cell are arranged adjacent eachother in a particular fashion to form a square-shaped n-p-n-p-n ESDprotection structure which provides a low impedance current dischargepath from many locations therein. Accordingly, the square-shaped ESDprotection structure thus formed has an enhanced current handlingcapability. Advantageously, the number of standard cells used toconstruct a square-shaped ESD protection structure may be varied at willto increase or decrease the amount of the current that is discharged.

Some embodiments of the present invention have a variable triggervoltage. To achieve trigger voltage variability, the base terminal ofeach of the npn transistors is coupled to a network consisting of a pairof back-to-back zener diodes connected in series with a resistor.Depending on the polarity of the applied ESD pulse, one of the zenerdiode pairs turns on thereby to generate current to the resistorconnected thereto. The voltage developed across the resistor raises thebase-emitter voltage of the npn transistor coupled thereto, therebytriggering the ESD protection structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a cross-sectional view of a lateral SCR device as known inthe prior art.

FIG. 1B shows a circuit schematic view of the lateral SCR device of FIG.1A.

FIG. 1C shows the current-voltage characteristic of the lateral SCRdevice of FIG. 1A.

FIG. 1D shows a top view of the lateral SCR device of FIG. 1A.

FIG. 2 shows the various semiconductor regions of the two terminaldual-direction ESD protection structure, in accordance with the presentinvention.

FIG. 3 shows a cross-sectional view of the dual-direction ESD protectionstructure of the present invention, fabricated in a standard CMOSprocess technology.

FIG. 4 shows a circuit schematic view of the ESD protection structure ofFIG. 3.

FIG. 5 is a composite of the cross-sectional and the circuit schematicviews of FIGS. 3 and 4.

FIG. 6 shows the current-voltage characteristic of the ESD protectionstructure of the present invention.

FIG. 7 shows a top view of the dual-direction ESD protection structureof FIG. 3 as well as the path of a current flow between adjacent p-baseregions thereof during an ESD pulse.

FIG. 8A shows a top view of a corner cell forming the corner regions ofa current-enhanced ESD protection structure, in accordance with thepresent invention.

FIG. 8B shows a cross sectional view of the corner cell of FIG. 10A.

FIG. 9A shows a top view of a center cell forming the center regions ofa current-enhanced ESD protection structure, in accordance with thepresent invention.

FIG. 9B shows a cross sectional view of the center cell of FIG. 9A.

FIG. 10A shows a top view of an edge cell forming the edges of acurrent-enhanced ESD protection structure, in accordance with thepresent invention.

FIG. 10B shows a cross sectional view of the edge cell of FIG. 10A.

FIG. 11A shows a top view of a first embodiment of a current-enhancedESD protection structure, in accordance with the present invention,constructed using the corner cell, the center cell and the edge cells ofFIGS. 8A, 9A and 10A.

FIG. 11B FIG. 11A shows a top view of a second embodiment of acurrent-enhanced ESD protection structure, constructed using the cornercell, the center cell and the edge cells of FIGS. 8A, 9A and 10A.

FIG. 12 shows a composite of a cross-sectional view and a circuitschematic view of a first embodiment of a variable trigger voltage ESDprotection structure, in accordance with the present invention.

FIG. 13 shows a circuit schematic view of the variable trigger voltageESD protection structure of FIG. 12.

FIG. 14 shows a circuit schematic view of a second embodiment of avariable trigger voltage ESD protection structure of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

A dual-direction Electro-Static Discharge (ESD) protection structure 50,in accordance with the present invention, is shown in FIG. 2. ESDprotection structure 50 is composed of three n-type semiconductorregions 52, 56 and 60 and two p-type semiconductor regions 54 and 58.P-type region 54 is disposed between n-type regions 52 and 56. P-typeregion 58 is disposed between n-type regions 56 and 60. Consequently,structure 50 is formed by an alternating arrangement of adjacentn-p-n-p-n semiconductor regions. Anode terminal A is in electricalcontact with n-type region 52 and cathode terminal K is in electricalcontact with n-type region 60.

FIG. 3 shows a cross sectional view of ESD protection structure 100 ofthe present invention, fabricated using a standard CMOS processtechnology. P-base 114 is disposed between n⁺ region 112 and n-well 116.Similarly, p-base 118 is disposed between n⁺ region 120 and n-wellregion 116. Anode terminal A is formed over and is in electrical contactwith n⁺ region 112 and p⁺ region 122. Cathode terminal K is formed overand is in electrical contact with n⁺ region 120 and p⁺ region 124. As isseen from FIG. 3, structure 100 has a symmetrical geometrical construct.Hence, a cut along line BB in FIG. 3 divides structure 100 into twophysically indistinguishable parts. Because of this symmetry, ESDprotection structure 100 operates without regard to the polarity of anESD pulse appearing across its two terminals A and K, thereby, renderingthe two terminals A and K fully interchangeable. CMOS technologyfabrication processing steps required to manufacture embodiment 100 arewell known in the art.

FIG. 4 shows a circuit schematic view of embodiment 100 of the presentinvention. Concurrent referrals to FIGS. 3 and 4 assist the reader inunderstanding the discussion below. N⁺ region 112, p-base 114 and n-well116 of FIG. 3 form the emitter, the base and the collector regions ofnpn bipolar transistor 130 of FIG. 4, respectively. N⁺ region 120,p-base 118 and n-well 116 of FIG. 3 form the emitter, the base and thecollector regions of npn bipolar transistor 150 of FIG. 4, respectively.N-well 116 forms the base region of pnp bipolar transistor 140.

If a positive voltage or current pulse is applied across terminals A andK of ESD protection structure 100, pnp transistor 140 and npn transistor150 turn on while npn transistor 130 remains off. Accordingly, p-base118 forms the collector region of pnp transistor 140 and p-base 114forms the emitter region of transistor 140, shown in FIG. 4 by solidarrow 142.

If a negative voltage or current pulse is applied across terminals A andK of ESD protection structure 100, pnp transistor 140 and npn transistor130 turn on while npn transistor 150 remains off. Accordingly p-base 114forms the collector region of pnp transistor 140 and p-base 118 formsthe emitter region of transistor 140, shown in FIG. 4 by hollow arrow144.

Resistor 132 represents the resistance of the p-base 114 disposedbetween p⁺ region 122 and n-well 116. Resistors 134 and 136 representthe resistances of the n-well region 116. Resistor 134 is located acrossthe base region of transistor 140 and the collector region of transistor130 and resistor 136 is located across the base region of transistor 140and the collector region of transistor 150. Resistor 138 represents theresistance of the p-base 118 disposed between p⁺ region 124 and n-well116.

FIG. 5 shows the circuit schematic view of FIG. 4 superimposed on thecross-sectional view of FIG. 3. FIG. 5 assists the reader inunderstanding the operation of ESD protection structure 100 of thepresent invention.

Referring to FIG. 5, when a positive pulse is applied across terminals Aand K, transistors 140 and 150 turn on. Thereafter thyristor 170,defined by p-n-p-n regions 114, 116, 118 and 120 (only a portion ofwhich is shown in FIG. 5), is triggered into a snap-back mode.Alternatively, when a negative pulse is applied between terminals A andK, transistors 140 and 130 turn on. Subsequently, thyristor 180 definedby p-n-p-n regions 118, 116, 114 and 112 (only a portion of which isshown in FIG. 5), is triggered into a snap-back mode. Only the operationof ESD protection structure 100 during an application of a positive ESDpulse across terminals A and K is discussed. The operation of ESDstructure 100 when a negative pulse is applied across terminals A and Kcan be easily inferred due to ESD protection structure 100's symmetry.

Referring to FIG. 5, when a positive ESD pulse appears across terminalsA and K, p-n junction 128 formed between regions 114 and 116 isforward-biased and p-n junction 126 formed between regions 118 and 116is reverse-biased. When the applied reverse bias across junction 126exceeds a threshold value, junction 126 enters into a reverse breakdownregion thereby generating electron-hole pairs. The holes thus generatedaccelerate toward p⁺ region 124 and are collected by terminal K. As theholes drift toward p⁺ region 124, a voltage potential develops acrossresistor 138 between nodes N1 and N2. Because p⁺ region 124 and n⁺region 120 are both connected to terminal K, the voltage across nodes N1and N2 also appears across nods N1 and N3. When the voltage across nodesN1 and N3 exceeds a certain value, the base-to-emitter junction of npnbipolar transistor 150 is forward-biased thereby turning on npntransistor 150.

As is seen from FIG. 5, resistor 136 is connected across the collectorregion of transistor 150 and the base region of transistor 140.Therefore, as transistor 150 turns on, the collector current oftransistor 150, which provides the current to the base region of pnptransistor 140, increases. Subsequently, as the voltage across thebase-emitter junction of transistor 140 falls below a certain limit,transistor 140 turns on. Once both transistors 150 and 140 are turnedon, thyristor 170 is triggered into a snap-back mode, resulting in theformation of a very low impedance path between terminals A and K todischarge the ESD current, thereby, to protect the IC against thepotential damages of the ESD pulse.

FIG. 6. shows the current-voltage (I-V) characteristic of a p-n-p-nthyristor 170 of FIG. 5. As the voltage across the two terminals ofthyristor 170 increases, the current flow through thyristor 170increases until the point marked by the I-V coordinates (I_(t), V_(t)),known in the art as the trigger point, is reached. If the voltage acrossthe two terminals increases beyond the trigger voltage, the thyristorenters into a snap-back mode. Thereafter, a low impedance path betweenthe two terminals is formed requiring a much lower voltage to sustainthe current flow. Consequently, the voltage across the p-n-p-n devicedecreases to a new value V_(h), commonly known in the art as the holdingvoltage. The I-V coordinates of the holding point are shown in FIG. 6 as(I_(h), V_(h)). Once the holding voltage is reached, any increase in thevoltage across the p-n-p-n device results in a sharp increase in thecurrent through the device. As is seen from FIG. 6, the slope of the I-Vcharacteristic of the device beyond the holding point is very sharp,signifying the high conductance of the device in this deep snap-backregion.

The I-V characteristic of the p-n-p-n device between the trigger voltageV_(t) and the holding voltage V_(h) has a negative slope, indicating thefact that the device exhibits a negative resistance in this region.

Both the trigger voltage and the holding voltage are importantparameters in the operation of a p-n-p-n device. The trigger voltagemust be exceeded before the snap-back occurs, and the holding voltagemust be exceeded before the device exhibits a very low resistance. Insome embodiments of the present invention the resistance exhibitedbeyond the holding voltage is approximately 1 to 2 ohms.

Referring to FIG. 5, the low impedance current discharge path acrossterminals A and K of ESD protection structure 100 during an appliedpositive voltage/current ESD pulse is as follows. The current flows fromterminal A, through resistor 132, into the emitter and the collectorregions of transistor 140 and, subsequently, into the base region oftransistor 150. Thereafter, the current enters the emitter region oftransistor 150 and finally exits structure 100 through terminal K.

When a negative voltage/current ESD pulse appears across terminals A andK of ESD protection structure 100, thyristor 180 is triggered into asnap-back region. The resulting low impedance current discharge pathformed between terminals A and K is as follows. The ESD current flowsfrom terminal K and after passing through resistor 138, flows into theemitter and the base regions of transistor 140 and, subsequently, entersinto the collector region of transistor 130. Thereafter, the currententers into the emitter region of transistor 130 and finally exitsstructure 100 through terminal A.

Therefore, a single ESD protection structure 100, in accordance with thepresent invention, advantageously provides protection against bothpositive and negative ESD pulses.

FIG. 7 shows a top view of the ESD protection structure 100 of thepresent invention. When an ESD pulse arrives between terminals A and K,current flows between p-base 114 and p-base 118 across section 126 ofn-well 116, as shown by solid arrows 130. Therefore, as is seen fromFIG. 7, the amount of the current flow is limited to that which crossesonly a single edge of each of the p-base regions 114 and 118. In orderto increase the amount of current handling capability—hence to increasethe ESD protection—prior art techniques add more p-base regions 114 or118 so as to allow for the addition of more rectangle-shaped p⁺ and n⁺regions, which are commonly referred to in the art as finger structures.The conventional technique of adding more p⁺ and n⁺ fingers, gives riseto a significant increase in the amount of the substrate surface areaconsumed without a proportional increase in the ESD protection of theresulting structure. Therefore, it is important to develop an ESDprotection structure which more efficiently utilizes the substratesurface area to provide a current handling capability that is greaterthan those known in the prior art.

In accordance with the present invention, to increase the currenthandling capability and hence the degree of ESD protection that a givenarea of a substrate surface provides, three building block cells, namelya corner cell, a center cell and an edge cell are developed. FIGS.8A-10A and 8B-10B show the top views and the cross-sectional views of acorner cell 300, a center cell 400 and an edge cell 500, respectively.The top views of the three building block cells have square geometricalshapes with identical areas.

From FIG. 8A it is seen that corner cell 300 provides current floweither to or from P⁺ region 124 along the two directions marked by solidarrows 130 and 132. From FIG. 9A, it is seen that center cell 400provides current flow either to or from P⁺ region 124 along the fourdirections marked by solid arrows 130, 132, 134 and 136. From FIG. 10Ait is seen that edge cell 500 provides current flow either to or from P⁺region 124 along the two directions marked by solid arrows 130 and 132.As their names imply, corner cell 300, center cell 400 and edge cell 500are disposed in the corner locations, the center locations and the edgelocations of a current-enhanced square-shaped ESD protection structure,in accordance with the present invention.

FIG. 11A shows a top view of embodiment 600 of the current-enhanced ESDprotection structure of the present invention. Embodiment 600 iscomposed of four center cells 300, four corner cells 400 and eight edgecells 500. Because of the identical sizes of the cells, embodiment 600has a square shape. Solid arrows 130 in FIG. 11A designate the junctionsacross which currents flow during an ESD pulse. As is seen from FIG. 11,depending on the cell types, the current flow between adjacent cellsoccurs along either two, three or four directions. In contrast, the ESDprotection structure of FIG. 7, constructed using conventional layouttechniques, provides a current flow between adjacent cells along onlyone direction. Therefore, ESD protection structure 600 has an enhancedcurrent handling capability and, as such, given identical substratesurface areas, provides a substantially greater degree of ESD protectionthan does ESD protection structure 100 of FIG. 7.

Advantageously, because of the square geometrical shapes and the modularconstruct of the building block cells, it is possible to vary the degreeof ESD protection desired by merely increasing or decreasing the numberof such cells used in forming a current-enhanced ESD protectionstructure. For instance, if a smaller current handling capability andESD protection is adequate, four corner cells 300, one center cell 400and four edge cells 600 are used to construct a current enhanced ESDprotection structure, as shown in FIG. 11B.

As discussed above, the trigger voltage of ESD protection structure 100of FIG. 5 is determined by the reverse breakdown voltage of junction126, which typically varies from 15 to 20 volts. The trigger voltage ofstructure 100 is varied by changing the concentration and the profile ofthe impurities in n-well 116 and p-base 118 regions. However, it isoften not possible to vary the parameters of a CMOS manufacturingprocess technology in order to change the trigger voltage of an ESDprotection structure formed thereby. Therefore, alternative methods ofadjusting the trigger voltage of an ESD protection device is needed.

FIG. 12 shows a super-imposition of a cross-sectional view and a circuitschematic view of ESD protection structure 700 of the variable triggervoltage ESD protection structure of the present invention. ESDprotection structure 700 is formed by coupling circuit 750 to ESDprotection structure 100 of FIG. 5.

FIG. 13 shows a circuit schematic view of ESD protection structure 700of the present invention. As is seen from FIG. 13, circuit 750 includesbranches 780 and 790. Branch 780 includes current source 770 andresistor 756, and branch 790 includes current source 772 and resistor758. Current source 770 is connected across terminal A and the baseterminal of transistor 150. Resistor 756 is connected across terminal Kand the base terminal of transistor 150. Current source 772 is connectedacross terminal K and the base terminal of transistor 130. Resistor 758is connected across terminal A and the base terminal of transistor 130.The operation of embodiment 700 is discussed next and is best understoodby referring to FIG. 12.

When a positive voltage/current pulse is applied across terminals A andK, current source 770 is activated and provides current to resistor 756thereby forward-biasing the base-to-emitter voltage of npn transistor150 and forcing transistor 150 and, subsequently, transistor 140 to turnon. Thereafter, thyristor 170 is triggered into a snap-back mode therebyto form a low impedance current discharge path between terminals A andK.

By varying the amount of current generated by current sources 770 and772 as well as by changing the resistances of resistors 756 and 758, thetrigger voltage of embodiment 700 is varied. Therefore, ESD protectionstructure 700 advantageously has a variable trigger voltage.

When a negative pulse is applied between terminals A and K, currentsource 772 forces transistor 130 to turn on, triggering thyristor 180into a snap-back mode and thereby forming a low-impedance discharge pathbetween terminals A and K.

FIG. 14 shows a variable trigger voltage ESD protection structure 800 ofthe present invention. ESD protection structure 800 is formed bycoupling circuit 850 to ESD protection structure 100. In ESD protectionstructure 800, back-to-back zener diode pair 852 and 854 act as acurrent source in branch 880 and back-to-back zener diode pair 860 and862 act as a current source in branch 890. Branch 880 is composed ofzener diodes 852 and 854, and resistor 856 which is connected across thebase terminal of transistor 150 and the cathode terminal K. Branch 890is composed of zener diodes 860 and 862, and resistor 858 which isconnected across the base terminal of transistor 130 and the anodeterminal A. The operation of structure 800 is discussed next.

When a positive voltage/current pulse is applied across terminals A andK, the voltage across diode 852 increases until diode 852 enters areverse breakdown region to thereby act as a current source.Concurrently, diode 854 is forward biased to provide a voltage drop ofnearly 0.65 volts across its two terminals. When diode 852 enters areverse breakdown region transistors 140 and 150 turn on, and,subsequently, structure 800 is triggered into a snap-back mode therebyto form a low impedance current discharge path between terminals A andK, as discussed above.

Advantageously, during the time period when diode 852 enters a reversebreakdown region, because of the presence of resistor 858 in branch 890,diode 860 does not enter a reverse breakdown region and, as such, nocurrent flows through branch 890, preventing transistor 130 from beingturned on.

when a negative voltage/current pulse is applied across terminals A andK, diode 862 enters a reverse breakdown region while diode 860 isforward-biased, forcing transistors 130 and 140 to turn on to therebytrigger structure 800 into a snap-back mode to discharge the current.Consequently, circuit 850 ensures that during an ESD pulse, a currentflows either in branch 880—in order to trigger a snap-back betweentransistors 140 and 150—or in branch 890—in order to trigger a snap-backbetween transistors 140 and 130—but not both.

The trigger voltage of ESD protection structure 800 is, therefore,approximately equal to the reverse breakdown voltage of the zener diodeswhich is much smaller than the reverse break-down voltage of junction126 of FIG. 5.

The exemplary embodiments of the invention described above areillustrative and not limitative. Other embodiments of this invention areobvious to those skilled in the art and are intended to fall within thescope of the appended claims.

1-20. (canceled)
 21. A method comprising: providing an electrostaticdischarge (ESD) protection structure in an integrated circuit formedfrom a semiconductor body having a substrate region of a firstconductivity type wherein the ESD protection structure comprises (a) afirst semiconductor region of a second conductivity type connected to afirst terminal, the second conductivity type being opposite to the firstconductivity type, (b) a second semiconductor region of the firstconductivity type connected to the first terminal and continuous withthe first semiconductor region, (c) an electrically floating thirdsemiconductor region of the second conductivity type continuous with thesecond semiconductor region and separated from the first semiconductorregion by the second semiconductor region, (d) a fourth semiconductorregion of the first conductivity type connected to a second terminal,continuous with the third semiconductor region, spaced apart from thefirst semiconductor region, and separated from the second semiconductorregion by the third semiconductor region, and (e) a fifth semiconductorregion of the second conductivity type connected to the second terminal,continuous with the fourth semiconductor region, spaced apart from thefirst and second semiconductor regions, and separated from the thirdsemiconductor region by the fourth semiconductor region, the second andfourth semiconductor regions being separated from the substrate regionby the third semiconductor region; and subjecting the integrated circuitto a voltage of magnitude greater than a trigger value such that (a) thevoltage is placed across the terminals, (b) current dissipating thevoltage automatically flows through the ESD protection structure whenthe voltage is placed across the terminals, and (c) current starts toflow from either terminal through the ESD protection structure to theother terminal substantially only when the voltage reaches or exceedsthe trigger value.
 22. A method as in claim 21 wherein the voltageacross the terminals arises from ESD between the terminals.
 23. A methodas in claim 21 wherein the ESD protection structure enters a snap-backcondition when the magnitude of the voltage across the terminals becomesgreater than the trigger value.
 24. A method as in claim 21 wherein: thesemiconductor body has a major surface to which the first through fifthsemiconductor regions extend; the second semiconductor regionsubstantially surrounds the first semiconductor region except along themajor surface; and the fourth semiconductor region substantiallysurrounds the fifth semiconductor region except along the major surface.25. A method as in claim 24 wherein the third semiconductor regionsubstantially surrounds the second and fourth semiconductor regionsexcept along the major surface.
 26. A method as in claim 21 wherein theproviding act includes providing each of the second and fourthsemiconductor regions to comprise a main portion and a contact portionmore heavily doped than the main portion such that the contact portionsof the second and fourth semiconductor regions respectively contact thefirst and second terminals.
 27. A method as in claim 26 wherein thecontact portion of the second semiconductor region is spaced apart fromthe first semiconductor region, and the contact portion of the fourthsemiconductor region is spaced apart from the fifth semiconductorregion.
 28. A method as in claim 26 wherein: the semiconductor body hasa major surface to which the first through fifth semiconductor regionsextend; the second semiconductor region substantially surrounds thefirst semiconductor region except along the major surface; and thefourth semiconductor region substantially surrounds the fifthsemiconductor region except along the major surface.
 29. A method as inclaim 28 wherein: the main portion of the second semiconductor regionalso substantially surrounds its contact portion except along the majorsurface; and the main portion of the fourth semiconductor region alsosubstantially surrounds its contact portion except along the majorsurface.
 30. A method as in claim 28 wherein the third semiconductorregion substantially surrounds the second and fourth semiconductorregions except along the major surface.
 31. A method comprising:providing an electrostatic discharge (ESD) protection structure in anintegrated circuit formed from a semiconductor body having a substrateregion of a first conductivity type wherein the ESD protection structurecomprises (a) a first semiconductor region of a second conductivity typeconnected to a first terminal, the second conductivity type beingopposite to the first conductivity type, (b) a second semiconductorregion of the first conductivity type connected to the first terminaland continuous with the first semiconductor region, (c) an electricallyfloating third semiconductor region of the second conductivity typecontinuous with the second semiconductor region and separated from thefirst semiconductor region by the second semiconductor region, (d) afourth semiconductor region of the first conductivity type connected toa second terminal, continuous with the third semiconductor region,spaced apart from the first semiconductor region, and separated from thesecond semiconductor region by the third semiconductor region, and (e) afifth semiconductor region of the second conductivity type connected tothe second terminal, continuous with the fourth semiconductor region,spaced apart from the first and second semiconductor regions, andseparated from the third semiconductor region by the fourthsemiconductor region, the second and fourth semiconductor regions beingseparated from the substrate region by the third semiconductor region;and subjecting the integrated circuit either to a first voltage ofmagnitude greater than a first trigger value or to a second voltage ofmagnitude greater than a second trigger value such that (a) the first orsecond voltage is placed across the terminals, (b) the first voltagecauses the first terminal to be at higher potential than the secondterminal, (c) the second voltage causes the second terminal to be athigher potential than the first terminal, (d) current dissipating thefirst or second voltage automatically flows through the ESD protectionstructure when the first or second voltage is placed across theterminals, and (e) current starts to flow from either terminal throughthe ESD protection structure to the other terminal substantially onlywhen the first voltage reaches or exceeds the first trigger value orwhen the second voltage reaches or exceeds the second trigger value. 32.A method as in claim 31 wherein the first or second voltage arises fromESD between the terminals.
 33. A method as in claim 31 wherein the ESDprotection structure enters a snap-back condition when the magnitude ofthe first voltage becomes greater than the first trigger value or whenthe magnitude of the second voltage becomes greater than the secondtrigger value.
 34. A method as in claim 31 wherein: the semiconductorbody has a major surface to which the first through fifth semiconductorregions extend; the second semiconductor region substantially surroundsthe first semiconductor region except along the major surface; and thefourth semiconductor region substantially surrounds the fifthsemiconductor region except along the major surface.
 35. A method as inclaim 34 wherein the third semiconductor region substantially surroundsthe second and fourth semiconductor regions except along the majorsurface.
 36. A method as in claim 31 wherein the providing act includesproviding each of the second and fourth semiconductor regions tocomprise a main portion and a contact portion more heavily doped thanthe main portion such that the contact portions of the second and fourthsemiconductor regions respectively contact the first and secondterminals.
 37. A method as in claim 36 wherein the contact portion ofthe second semiconductor region is spaced apart from the firstsemiconductor region, and the contact portion of the fourthsemiconductor region is spaced apart from the fifth semiconductorregion.
 38. A method as in claim 36 wherein: the semiconductor body hasa major surface to which the first through fifth semiconductor regionsextend; the second semiconductor region substantially surrounds thefirst semiconductor region except along the major surface; and thefourth semiconductor region substantially surrounds the fifthsemiconductor region except along the major surface.
 39. A method as inclaim 38 wherein: the main portion of the second semiconductor regionalso substantially surrounds its contact portion except along the majorsurface; and the main portion of the fourth semiconductor region alsosubstantially surrounds its contact portion except along the majorsurface.
 40. A method as in claim 38 wherein the third semiconductorregion substantially surrounds the second and fourth semiconductorregions except along the major surface.
 41. A method as in claim 31wherein: the current flows from the first terminal substantially throughthe second, third, fourth, and fifth semiconductor regions to the secondterminal when the first voltage exceeds the first trigger value; and thecurrent flows from the second terminal substantially through the fourth,third, second, and first semiconductor regions to the first terminalwhen the second voltage exceeds the second trigger value.
 42. A methodas in claim 31 wherein the third semiconductor region forms, with thefourth and second semiconductor regions, respective pn junctions havingrespective reverse breakdown voltages whose magnitudes respectivelydetermine the first and second trigger values.
 43. A method as in claim21 wherein current continues to flow from either terminal through theESD protection structure to the other terminal when the voltage dropsbelow the trigger value after current starts to flow from eitherterminal through the ESD protection structure to the other terminalsubstantially only when the voltage exceeds the trigger value.
 44. Amethod as in claim 21 wherein the trigger value is a trigger value of,and is defined by characteristics of, the ESD protection structure. 45.A method as in claim 31 wherein current continues to flow from eitherterminal through the ESD protection structure to the other terminal whenthe first voltage drops below the first trigger value or when the secondvoltage drops below the second trigger value current after starts toflow from either terminal through the ESD protection structure to theother terminal respectively substantially only when the first voltageexceeds the first trigger value or when the second voltage exceeds thesecond trigger value.
 46. A method as in claim 31 wherein each triggervalue is a trigger value of, and is defined by characteristics of, theESD protection structure.